1. Field of the Invention
The present invention relates to a process for manufacturing a memory device, in particular a phase change memory, including a silicidation step.
2. Description of the Related Art
As is known, phase change memory cells utilize a class of materials that have the unique property of being reversibly switchable from one phase to another with measurable distinct electrical properties associated with each phase. For example, these materials may change between an amorphous disordered phase and a crystalline, or polycrystalline, ordered phase. A material property that may change and provide a signature for each phase is the material resistivity, which is considerably different in the two states.
At present, alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can advantageously be used in phase change cells. The currently most promising chalcogenide is formed by a Ge, Sb and Te alloy (Ge2Sb2Te5), which is currently widely used for storing information in overwritable disks.
In chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous phase (more resistive) to the polycrystalline phase (more conductive) and vice versa, as shown in FIG. 1. Furthermore, in the amorphous phase, resistivity strongly depends also on temperature, with variations of one order of magnitude every 100° C., with a behavior similar to that of P-type semiconductor materials.
Phase change may be obtained by locally increasing the temperature, as shown in FIG. 2. Below 150° C. both phases are stable. Above 200° C. (temperature of start of nucleation, designated by Tx), fast nucleation of the crystallites takes place, and, if the material is kept at the crystallization temperature for a sufficient length of time (time t2), it changes its phase and becomes crystalline. To bring the chalcogenide back into the amorphous state, it is necessary to raise the temperature above the melting temperature Tm (approximately 600° C.) and then to cool the chalcogenide off rapidly (time t1).
From the electrical standpoint, it is possible to reach both critical temperatures, namely the crystallization and the melting temperatures, by causing a current to flow through a resistive element which heats the chalcogenic material by Joule effect.
The basic structure of a PCM element 1 which operates according to the principles described above is shown in FIG. 3 and comprises a first electrode 2 of resistive type, forming a heater, a programmable element 3 and a second electrode 5. The programmable element 3 is made of a chalcogenide and is normally in the polycrystalline state at the completion of processing. One part of the programmable element 3 is in direct contact with the first electrode 2 and forms the active portion affected by phase change, referred to as the phase change portion 4.
The use of the PCM element 1 of FIG. 3 has been already proposed to form memory cells. To avoid noise caused by adjacent cells, the PCM element 1 is generally coupled with a selection element, such as a MOS transistor or a bipolar transistor.
Furthermore, the PCM cells, forming a memory array, should be integrated with circuitry for controlling operation thereof. A manufacturing process compatible with a standard CMOS flow has been already proposed in U.S. application Ser. No. 10/313,991, filed Dec. 5, 2002, entitled “Small area contact region, high efficiency phase change memory cell, and fabrication method thereof”.
According to this process and referring to FIG. 4, a wafer 10 comprises an array portion 50 and a circuitry portion 51 and includes a substrate 7 and an epitaxial layer 8. First, the wafer 10 is subject to initial manufacturing steps to define active areas in the epitaxial layer 8. To this end, field insulating regions 13 are formed within the substrate, e.g., using the “shallow trench” technology. Then, in the array portion 50, buried subcollector regions 9 of P+-type are implanted to extend down to the substrate 7. After annealing, in the circuitry portion 51, N-wells 18 and P-wells 19 are implanted, using separate masks. Furthermore, doping of the channels of the periphery transistors is carried out.
Thereafter, an oxide layer 20 is grown onto the entire surface of the wafer 10 and a polysilicon layer is deposited. The polysilicon layer is then defined, to form gate electrodes 16 of the periphery transistors. After source and drain reoxidation, LDD implants are carried out for both P-channel and N-channel periphery transistors, to form P-type, light doped regions 40 and analogous, N-type light doped regions 44.
Then, a silicide protection mask (not shown) is formed over the array portion; an oxide layer is deposited onto the whole wafer 10 and etched, to form spacers 41 on the sides of the gate electrodes 16; source and drain regions 42 for the periphery transistors are implanted and self-aligned silicide regions 43 are grown over the gate electrodes 16 and the source and drain regions 42.
After removing the silicide protection mask, collector regions 11 of P-type and base regions 12 of N-type are implanted over the buried subcollector regions 9; then a nitride layer 45 is deposited.
Thereafter, a dielectric layer 21 is deposited and planarized. Then dielectric layer 21 and nitride layer 45 are etched where contact are to be formed so as to uncover portions of silicide regions 43 and base region 12.
Then, in a manner not shown, a base contact region 15 of N+-type and, subsequently, an emitter region 14 of P+-type are implanted into base region 12. Thus, the structure of FIG. 4 is obtained.
Thereafter, the first electrode 2 and the programmable element 3 of FIG. 3 are formed, to provide a sub-lithographic contact area.